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SEMICONDUCTOR
SYNERGY
256 x 4 ECL RAM
SY100422-3/4/5/7 SY101422-3/4/5/7
SY10422-3/4/5/7 SY100422-3/4/5/7 SY10422-3/4/5/7 SY101422-3/4/5/7
FEATURES
s s s s s s s s s s s s s s Address access time, tAA: 3/4/5/7ns max. Block select access time, tAB: 2ns max. Write pulse width, tWW: 3ns min. Edge rate, tr/tf: 500ps typ. Write recovery times under 5ns Power supply current, IEE: -250mA, -200mA for -5/7ns Superior immunity against alpha particles provides virtually no soft error sensitivity Built with advanced ASSETTM technology Fully compatible with industry standard 10K/100K ECL I/O levels Noise margins improved with on-chip voltage and temperature compensation Open emitter output for easy memory expansion Includes popular Block Select function allowing individual read/write control over blocks ESD protection of 2000V Available in 24-pin flatpack and 28-pin PLCC and MLCC packages
DESCRIPTION
The Synergy SY10/100/101422 are 1024-bit Random Access Memories (RAMs), designed with advanced Emitter Coupled Logic (ECL) circuitry. The devices are organized as 256-words-by-4-bits and meet the standard 10K/100K family signal levels. The SY100422 is also supply voltagecompatible with 100K ECL, while the SY101422 operates from 10K ECL supply voltage (-5.2V). All feature on-chip voltage and temperature compensation for improved noise margin. The SY10/100/101422 employ proprietary circuit design techniques and Synergy's proprietary ASSET advanced bipolar technology to achieve extremely fast access, write pulse width and write recovery times. ASSET uses proprietary technology concepts to achieve significant reduction in parasitic capacitance while improving device packing density. Synergy's circuit design techniques, coupled with ASSET, result not only in ultra-fast performance, but also allow device operation at reduced power levels with virtually no soft error sensitivity and with outstanding device reliability in volume production.
BLOCK DIAGRAM
A0 A5 A6 A7
Y-Decoder/Driver
A2 A3 A4
X-Decoder/ Driver
A1
Memory Cell Array
WE
SA/WA*
SA/WA
SA/WA
SA/WA
DI0 BS0 DO0
* SA = Sense Amplifier WA = Write Amplifier
DI1 BS1 DO1
DI2 BS2 DO2
DI3 BS3 DO3
(c) 1999 Micrel-Synergy
Rev.: E
Amendment: /0
1
Issue Date: August,1999
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7 SY100422-3/4/5/7 SY101422-3/4/5/7
PIN CONFIGURATIONS
VEE A7
VCCA NC
A2
A1
A0
A6
DO0
DO3
VCC
BS0
A3 A4 DI2 DI3 BS2 DO2
1 2 3 4 5 6
24 23 22 21 20 19 18 17 Top View 16 Flatpack 15 F24-1 14 13 7 8 9 10 11 12 DO3 BS3 VCC VCCA DO0 BS0
4
3
2
1 28 27 26 25 24 DO2 BS2 DI3 NC DI2 A4 A3
A5 WE DI1 DI0 BS1 DO1
DO1 BS1 DI0 NC DI1 WE A5
5 6 7 8 9 10 11 Top View MLCC (M28-1) or PLCC (J28-1)
20 19 12 13 14 15 16 17 18
NC A0 A7 A1 A6 VEE A2
PIN NAMES
Label A0 - A7 BS0 - BS3 WE DI0 - DI3 DO0 - DO3 VCC VCCA VEE Function Address Inputs Block Select (BS) Write Enable Data Input (DIN) Data Output (DOUT) GND (0V) Output GND (0V) Supply Voltage
TRUTH TABLE
Input BS H L L L WE X L L H DIN X H L X Output L L L DOUT Mode Disabled Write "H" Write "L" Read
NOTE: H = High Voltage Level L = Low Voltage Level X = Don't Care
2
BS3
23 22 21
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7 SY100422-3/4/5/7 SY101422-3/4/5/7
FUNCTIONAL DESCRIPTION
The Synergy SY10/100/101422 are 1024-bit RAMs organized as four 256-by-1-bit blocks with each block having its own Block Select (BS) control signal that functions essentially like a unique chip select for the Block. The four blocks and Block Selects together make the device a 256 x 4-bit RAM. Memory cell selection is achieved by using the 8 address bits designated as A0 through A7. Each of the 28 possible input address combinations corresponds to a unique word location in memory. The active low Block Select (BS) control signals are provided for memory expansion and for independent control of each of the four 256 x 1-bit blocks of memory. The active low Write Enable (WE) controls the read and write operation on the selected block or blocks. Data resident on the DIN inputs (DI0 through DI3) is written into the addressed location only when WE and the Block Select (BS) associated with each of the DIN bits is held LOW. This allows control of the Write operation to any one, two, three or all four of the input data bits. In order to perform a read operation, WE is held high, the Block Select (BS) associated with each of the four output blocks is held low, and the non-inverted output data at the addressed location is transferred to DOUT (DO0 through DO3) to be read out. This allows control of the Read operation to any one, two, three or all four of the output blocks. Open emitter outputs are provided for maximum flexibility and memory expansion by allowing output wire-OR connections. External termination of 50 to -2.0V or an equivalent circuit must be used to provide the specified output levels. All outputs are forced to a logic LOW level when the RAM is being written into (WE = LOW). The output (or outputs) associated with a block (or blocks) of memory can be forced to a logic LOW low level by deselecting that block (or blocks) with its respective Block Select input (BS0 - BS3 = HIGH).
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VEE VIN IOUT TC Tstore Rating VEE Pin Potential to VCC Pin Input Voltage DC Output Current (Output High) Temperature Under Bias Storage Temperature Value +0.5 to -7.0 +0.5 to VEE -30 -55 to +125 -65 to +150 Unit V V mA C C
GUARANTEED OPERATING CONDITIONS
Parameter Supply Voltage(1) 10K 100K 101K Case Temperature Supply Voltage(1) Case Temperature Supply Voltage(1) Case Temperature
NOTE: 1. Referenced to VCC.
Symbol Min. VEE TC VEE TC VEE TC -5.46 0 -4.8 0 -5.46 0
Typ. -5.2 -- -4.5 -- -5.2 --
Max. Unit -4.94 75 -4.2 85 -4.94 85 V C V C V C
NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability.
RISE AND FALL TIME
Parameter Output Rise Time Output Fall Time Code(1) Symbol Min. Typ. Max. Unit F S F S tr tf -- -- 500 1500 500 1500 -- -- ps ps
CAPACITANCE
Parameter Input Pin Capacitance Output Pin Capacitance Symbol CIN COUT Min. -- -- Typ. 4 5 Max. -- -- Unit pF pF
NOTE: 1. F = Fast Edge Rate S = Standard Edge Rate
3
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7 SY100422-3/4/5/7 SY101422-3/4/5/7
10K DC ELECTRICAL CHARACTERISTICS
VCC = 0V; TC = 0C to +75C; VEE = -5.2V; Airflow > 2.5m/s; Output Load = 50 to -2.0V
Symbol VOH Parameter Output High Voltage TC 0C +25C +75C 0C +25C +75C 0C +25C +75C 0C +25C +75C 0C +25C +75C 0C +25C +75C 0C to+ 75C 0C to +75C 0C to +75C 0C to +75C 0C to +75C 0C to +75C Min. -1000 -960 -900 -1870 -1850 -1830 -1020 -980 -920 -- -- -- -1145 -1105 -1045 -1870 -1850 -1830 0.0 -2 30 40 -2 0.0 -250 -200 Max. -840 -810 -720 -1665 -1650 -1625 -- -- -- -1645 -1630 -1605 -840 -810 -720 -1490 -1475 -1450 20 2 170 220 35 60 -- -- Unit mV Condition VIN = VIH Max. or VIL Min.
VOL
Output Low Voltage
mV
VIN = VIH Max. or VIL Min.
VOHC
Output High Voltage
mV
VIN = VIH Min. or VIL Max.
VOLC
Output Low Voltage
mV
VIN = VIH Min. or VIL Max.
VIH
Input High Voltage
mV
Guaranteed Input Voltage High for All Inputs Guaranteed Input Voltage Low for All Inputs VIN = VIH Max. VIN = VIL Min. VIN = VIL Min. VIN = VIH Max. VIN = VIL Min. VIN = VIH Max. All Inputs and Outputs Open
VIL
Input Low Voltage
mV
IIH IIL IIL IIH IIL IIH IEE
Input High Current Input Low Current BS Input Low Current BS Input High Current WE Input Low Current WE Input High Current Power Supply Current
A A A A A A mA
-3ns, -4ns -5ns, -7ns 0C to +75C
100K/101K DC ELECTRICAL CHARACTERISTICS
VCCA = 0V VCC = 0V
Symbol VOH VOL VOHC VOLC VIH VIL IIH IIL IIL IIH IIL IIH IEE
VEE = -4.5V (100K) VEE = -5.2V (101K)
Parameter Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current BS Input Low Current BS Input High Current WE Input Low Current WE Input High Current Power Supply Current -3ns, -4ns -5ns, -7ns Min. -1025 -1810 -1035 -- -1165 -1810 0.0 -2 30 40 -2 0.0 -250 -200
TC = 0C to +85C
Max. -880 -1620 -- -1610 -880 -1475 20 2 170 220 35 60 -- -- Unit mV mV mV mV mV mV A A A A A A mA
Airflow > 2.5m/s Output Load = 50 to -2.0V
Condition VIN = VIH Max. or VIL Min. VIN = VIH Max. or VIL Min. VIN = VIH Min. or VIL Max. VIN = VIH Min. or VIL Max. Guaranteed Input Voltage High for All Inputs Guaranteed Input Voltage Low for All Inputs VIN = VIH Max. VIN = VIL Min. VIN = VIL Min. VIN = VIH Max. VIN = VIL Min. VIN = VIH Max. All Inputs and Outputs Open
4
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7 SY100422-3/4/5/7 SY101422-3/4/5/7
AC ELECTRICAL CHARACTERISTICS AC TEST CONDITIONS
VCC = VCCA = 0V VEE = -5.2V 5%(10K) VEE = -4.5V 0.3V(100K) VEE = -5.2V 5%(101K) Output Load = 50 to -2.0V TC = 0C to +75C (10K) TC = 0C to +85C (100K/101K) Airflow > 2.5m/s
TC 10K 0C +25C +75C 0C to +85C VIH -0.933V -0.90V -0.863V -0.90V VIL -1.733V -1.70V -1.663V -1.70V
Loading Condition
GND
100/101K
Input Pulse
VIH
VCCA VCC OUT VEE RL CL
80% 20% VIL tr
tr = tf = 1.0ns typ.
tf
0.01F VEE -2.0V
NOTE:
OUTPUT LOAD: RL = 50 CL = 5pF* (typ.) * (Modeled as 50 transmission line terminated to -2V.) All timing measurements referenced to 50% input levels.
READ CYCLE
SY10422-3 SY100422-3 SY101422-3 SY10422-4 SY100422-4 SY101422-4 SY10422-5 SY100422-5 SY101422-5 SY10422-7 SY100422-7 SY101422-7
Symbol tAA tAB tRB TAVQV TBSLQV TBSHQL
Parameter Address Access Time Block Select Access Time Block Select Recovery Time
Min. -- -- --
Max. 3 2 2
Min. -- -- --
Max. 4 2 2
Min. -- -- --
Max. 5 3 3
Min. -- -- --
Max. 7 3 3
Unit ns ns ns
READ CYCLE TIMING DIAGRAM
BS 50% tAB tRB 80% 50% 20% tr tf
DOUT Address 50% tAA 50%
DOUT
5
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7 SY100422-3/4/5/7 SY101422-3/4/5/7
READ CYCLE
SY10422-3 SY100422-3 SY101422-3 SY10422-4 SY100422-4 SY101422-4 SY10422-5 SY100422-5 SY101422-5 SY10422-7 SY100422-7 SY101422-7
Symbol tWW TWLWH tWS tWR tSA tSB tSD tHA tHB tHD TWLQL TWHQV TAVWL TBSLWL TDVWL TWHAX TWHBSX TWHDX
Parameter Write Pulse Width Write Disable Time Write Recovery Time Address Set-Up Time Block Select Set-Up Time Data Set-Up Time Address Hold Time Block Select Hold Time Data Hold Time
Min. 3 -- -- 1 0 0 1 1 1
Max. -- 3 3 -- -- -- -- -- --
Min. 4 -- -- 1 0 0 1 1 1
Max. -- 4 4 -- -- -- -- -- --
Min. 5 -- -- 1 1 1 1 1 1
Max. -- 4 4 -- -- -- -- -- --
Min. 5 -- -- 1 1 1 1 1 1
Max. -- 4 4 -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns
WRITE CYCLE TIMING DIAGRAM
BS
Address
DIN tSD WE tSA DOUT tSB tWS tWR 50% tWW tHB tHD
6
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7 SY100422-3/4/5/7 SY101422-3/4/5/7
PRODUCT ORDERING CODE
Edge Rate Fast Fast Fast Fast Standard Standard Standard Standard Package Type F24-1 M28-1 F24-1 M28-1 F24-1 J28-1 F24-1 J28-1 Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial
Speed (ns) 3 4 5 7
Ordering Code SY10/100/101422-3FCF SY10/100/101422-3MCF SY10/100/101422-4FCF SY10/100/101422-4MCF SY10/100/101422-5FCS SY10/100/101422-5JCS SY10/100/101422-7FCS SY10/100/101422-7JCS
7
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7 SY100422-3/4/5/7 SY101422-3/4/5/7
24 LEAD CERPACK (F24-1)
8
SEMICONDUCTOR
SYNERGY
SY10422-3/4/5/7 SY100422-3/4/5/7 SY101422-3/4/5/7
28 LEAD PLASTIC LEADED CHIP CARRIER (J28-1)
9

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